1. Field of the Invention
The present invention relates generally to serial data transmission. More particularly, the present invention relates to an apparatus and method which is used for transmitting data that is sourced with a high jitter clock signal in a serial data stream over a single fiber cable or wire.
2. Description of the Prior Art
SerDes or serializer/deserializer devices facilitate the transmission of parallel data in a serial format between two points over a single serial transmission line which reduces the number of data paths and the number of fiber cables or wires required.
When a digital clock is being transmitted with digital data, it is desirable not to have a second fiber cable for transmitting the digital clock. In this particular case, the digital clock is embedded into the digital data. Transmission circuits need to be designed with sufficient edge transitions so that the signal's receiving end can regenerate the digital clock.
It is very desirable to transmit the data with a clock that is very stable, that is a clock having low jitter. When the data for transmission includes a clock with very high jitter, it very difficult or impossible to receive the information.
The method normally used to transmit a digital clock with high jitter is to filter the clock prior to transmission.
The digital clock is filtered with a low pass filter or a phase lock loop which is a closed-loop feedback control system. Filtering using a low pass filter or a phase lock loop reduces some low frequency jitter, but does not provide a complete solution for removing jitter from a high frequency digital clock.
There is also a commercially available device which use phase lock loop technology along with a stabilized reference clock to attenuate jitter. However, this device only supports standard communication frequencies and does not support a non-standard communication frequency over a fiber cable.